The present invention relates to a method for detecting and locating faults in an electrical or electronic device or assembly and, more particularly, to a method for detecting and locating faults by the use of adaptive inference testing techniques.
In the field of electronics in general and in printed circuit board assembly in particular, electronic components are generally mounted, affixed, plugged into or otherwise associated with printed circuit boards. Such electronic components may be analog devices, digital devices, integrate circuits and the like.
The boards, in turn, usually have electrical contacts along one or more sides thereof for plugging into connectors. On a typical personal computer, for example, some five to ten boards are provided and are associated, by means of connectors, with a so-called mother board. Of course, more sophisticated machines would tend to have a greater number of boards and less sophisticated instruments would have tend to have fewer boards.
As the technology of electronic devices advances and as the consumer market for advanced products matures, not only does the functional complexity and the number of manufactured machines increase, but so too may the number of components per board increase. This makes it difficult to directly access all of the test points required to test a loaded board completely.
Finally, components mounted on the boards become ever more powerful and more difficult to test as new functions are required.
It therefore has become increasingly important to enhance procedures for testing proper operation of components, boards and machines. To the extent that such testing procedures can be improved, more efficient methods and more accurate methods are ensured.
For purposes of this description, the term "adaptive inference" means the ability to predict the cause of a previously unobserved fault from the relationships with other known fault information.
Also for purposes of this description, the term "unit under test (UUT)" is used to identify any component or assembly to be tested. Heretofore, UUTs were tested by technicians with the aid of certain instruments as simple as a voltmeter or as complex as a mainframe computer. Such testing methods were necessarily time consuming and labor intensive.
More recently, programmable systems have been used to test specific UUTs. These systems tend to be more efficient than manual methods, by allowing a greater number of UUTs to be tested in a given amount of time. But in order to use these programmable systems to test every possible condition of a component or board, every possible stimulant must be applied to the UUT and every possible response must be analyzed or at least compared with its associated proper reference response.
Even on a simple UUT, unanticipated problems can arise in many ways. Previous methods required a test engineer to program each of these possible faults into a machine. This required enormous amounts of programming. Over 25,000 lines of code and six months of effort were not unusual.
The present invention eliminates this programming effort for fault isolation by mathematically comparing a new fault to previously stored faults. A figure of merit is derived and displayed to indicate likely causes and closeness to known faults.
For instance, a certain circuit node may be shorted to ground and the faults recorded and stored in memory. When the same node is shorted to +5v, the acquired data is not going to be identical, but may be very close. In a traditional programming environment, two separate programs would be needed to cover both those cases: But the present invention indicates a high probability (figure of merit) that the indicated node is the source of the fault.
Powerful display tools in accordance with the present invention, such as waveform displays with color highlighting to show discrepancies, aid in localizing the troublesome area. A figure of merit less than 100% for faults never before experienced can signal the operator to investigate.
In the above example, when the operator discovers that a node is stuck high (not grounded), with a single keystroke the new fault can be added to memory. If the fault occurs again, the message displayed indicates this new fault with a high figure of merit: that same node is likely to be stuck to +5v. The next time the test is run with the same node stuck high, the system displays the message and indicates the second most likely diagnosis is the same node stuck low with a figure of merit less than 100%.
In this way, the system accumulates a representation of knowledge that it has gained in the past. It can infer things it has never seen. It operates similarly to the way that a human operator would debug a circuit. Moreover, the system improves with time and, of course, it never forgets.
A particularly vexing problem relates to the fact that faults that have not occurred before and therefore that have not been anticipated would often simply not be found either by the programmable test systems of the prior art or by the human technician. When such situations arise (i.e., when a fault occurs that was not contemplated), the conventional approach has been to replace components on the board systematically or even randomly, testing each removed component separately or testing the board as a whole after each component replacement.
The process of removing and replacing components is fraught with the possibility of adverse results. Removing a component from its position on the printed circuit board requires effort on the part of the human technician or of a machine. It may also require heating the pins of the component to desolder its connection to the board. The process must be reversed when the component is to be reattached to the board after testing. Thus, even if the component were acceptable before its test, there is a likelihood that it will no longer be acceptable thereafter.
When the board finally operates according to its specifications, however, the technician can safely assume that the component at fault was the one last replaced. While the result of this technique is to arrive at a properly operating component and board, a more efficient method for attaining the same result is needed.
U.S. Pat. No. 4,766,595 issued to Gollomp discloses a system for diagnosing faults in a UUT using behavior models to incorporate design knowledge of a UUT to run diagnostic tests. The system is capable of being used with automatic test equipment and providing test programs for automatic test. Test data is applied in a feedback arrangement to improve fault diagnosis.
U.S. Pat. No. 4,709,366 issued to Scott et al. discloses a system for isolating circuit faults in an electronic system and guides a technician node by node on a UUT to the source of failure. A computer provides stimulus patterns, and responses at the nodes are measured using a probe. A tailored signal for the node being probed is applied and the response is compared to a predetermined response and either a failure or probe next node response is generated. The computer displays clues to the technician to determine which node is most apt to be defective.
U.S. Pat. No. 4,847,795 issued to Baker et al. discloses a system for diagnosing electronic assembly defects. The system has a knowledge base for storing information on UUT and receiving current test failure. The system has a pattern search which compares current test data to stored information. A voting section recommends a repair process. The knowledge base is updated with information as to whether o not the repair eliminated the defect.
U.S. Pat. No. 4,841,456 issued to Hogan, Jr., et al. discloses a system in which an artificial intelligence system is interfaced with an automatic test system such that the actions of the AI are indistinguishable from those of a human operator. The automatic testing system includes an automatic test equipment controller, at least one test instrument and a UUT. There is a storage means for storing a functional test procedure (FTP) for the UUT. The FTP data set contains the results obtained by executing the FTP. An expert system means processes the FTP data and indicates when a failure has occurred and, if possible, the defective UUT portion that may have caused the failure. The expert system means produces output data identifying the defective UUT portion. The automatic test system may also comprise a diagnostic test procedure for the UUT should the expert system determine that further testing is required.
U.S. Pat. No. 4,857,833 issued to Gonzales et al, discloses a system which determines which of a plurality of electrical devices connected to a node of a circuit under test is causing a failure. The node is driven one device at a time and passive voltages at the node are taken for each device. The different device voltages are measured and analyzed to identify which device is causing the failure.
It would be advantageous to provide a system for detecting faults on a electronic assembly or component that have not occurred before.
It would also be advantageous to provide a system for detecting unanticipated faults by using adaptive inference techniques.
It would also be advantageous to provide a system for identifying the precise location of faults on a complex printed circuit board.
It would also be advantageous to provide a system for detecting faults in an electronic device and for displaying possible faults within the device.
It would also be advantageous to provide a method of detecting faults by reintroducing data from previously stored data to an electronic device under test.
It would also be advantageous to provide an adaptive inference test system to identify faults by applying a stimulus to an electronic device and observing displayed response test data.